Adc for hybrid energy in communication base stations

A final potential issue is the requirement for the same ADC design to be used in the transmitter feedback path. This feedback path is used to measure PA distortion and then apply digital pre-distortion (DPD) to avoid violating spectral masks.

The ADC power consumption is 641 mW at 5 GS/s, which consists of 299 mW for input buffers, bandgap, and clock receiver, 191 mW for the ADC core and clocking, and 151 mW for digital calibration. Measured performance in band 42 blocker test RF-sampling ADCs are becoming a viable alternative for conventional down-conversion receivers.

The ADC input signal contains a near full-scale blocker channel and 52.4 dB smaller desired channel separated by 5 MHz, both near 3.5 GHz. These are sampled at 4423.68 MS/s and then down-converted and decimated using on-chip digital logic.

Each ADC channel can operate up to 625 MS/s for an aggregate rate up to 5 GS/s. To achieve excellent spectral purity at back-off, two techniques are implemented. First, each ADC channel implements front-end chopping at the sampling stage.

Direct-RF analog-to-digital conversion has been an active research topic for many years. Recent technology and design advances have pushed these data converters from research to real-world deployment. We will discuss requirements and implementation of such an ADC, designed for direct-RF conversion in a wireless base-station.

Clearly, if the input signal is centered at 3.5 GHz, an input bandwidth of at least 4 GHz is required to maintain gain flatness and avoid phase distortion that would need to be corrected with digital equalization. Moreover, the ADC will be integrated with the rest of the receiver on board rather than on-die.